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ST2602B
8-bit Integrated Microcontroller
Note: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification. Some parameters are subject to change.
Datasheet
Version 1.1 2009/03/06
ST2602B
1
GENERAL DESCRIPTION
content. The clock of LCD (LCDCK) is not only sourced from main-frequency (OSC), it can also be sourced by OSCX (32KHz crystal) to make current consumption to be minimum. Besides, Vlcd has excellent voltage variation when Vdd changes from 2.4V to 3.6V. Further more, ST2602B has inside trimming fuse function for Vlcd and LVD.So every ST2602B real-chip will have almost the same default Vlcd and LVD voltage. The ST2602B equips 2 serial communication ports, one UART port and one SPI port, to perform different communications, ex.: RS-232 and IrDA, with system components or other products such as PC, Notebook, and popular PDA. Three clocking outputs can produce synthesized PWM signals or high frequency carrier for IR remote control. This helps products become more useful in our daily life. The built-in four-channel PSG are designed to generate key tone, melody, voice, and speech. Two dedicated pins with large driving capacity can drive a buzzer/speaker directly. The ST2602B has a Low Voltage Detector (LVD) for power management usage. The status of internal or external power can be detected and reported to the management software. Power bouncing during power-on is a major problem when designing a reliable system. The ST2602B equips a Low Voltage Reset function to keep the whole system in reset status when power is low. After the power returns to normal level, the system may recover its original states and keeps working correctly. With these integrated functions inside, the ST2602B single chip microcontroller is a right solution for PDA, translator, databank and other consumer products. The block diagram of ST2602B is shown in the following figure.
The ST2602B is a 8-bit integrated microcontroller designed with CMOS silicon gate technology. The true static CPU core, power down modes and dual oscillators design makes the ST2602B suitable for power saving and long battery life designs. The ST2602B integrates various logic to support functions on-chip which are needed by system designers. The ST2602B features the capacity of memory access of maximum 44M bytes and DMA function for fast memory transfer. Six chip-select pins are equipped for direct connection to external ROM, SRAM, Flash memory or other devices. The maximum size for a single external memory device can be 16M bytes. The ST2602B has 39 I/Os grouped into 5 ports. They are Port-C, Port-D, Port-E (7 pins), Port-F and Port-L, where the Port-F consists of 8 open-drain output pins shared with LCD COMs. Each I/O pins can be programmed to input or output individually. Port-C input pins provide both pull-up and pull-down options. The other input pins only support the pull-up option. In the case of output mode, Port-C output pins have open-drain type and CMOS type options; while the other ports are fixed at CMOS type. The Port-C/D/E/F/L are shared with other system functions. All the properties of the I/O pins are still programmable when they are configured as other special functional signals. This enlarges the flexibility of the usage of the functional signals. The ability of driving large LCD panels, up to 160x120 in BW mode, and hardware gray-level support may enrich the display information and the diversify the display contents as well. By the patented sharing mechanism design of internal memory, the LCD display function can be done without the need of external display RAM. The variable LCD buffer design also makes it feasible to use small internal display RAM as the buffer of large-sized display. User may free major internal RAM for computing or temporary access while keeping the display
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ST2602B
2
BLOCK DIAGRAM
VCC/GND TEST VIN
Low Voltage Detector
Low Voltage Reset RESET OSCI XIO OSCXI OSCXO A[22:0] D[7:0] RD WR PVCC/PGND PSGO/PSGOB MMD/CS0 CS5 ~ 1/PD4 ~ 0 CS6/A23/PD5 TCO0/PE0 TCO1/PE1 BCO/PE2 PE6~3 PF7~0 Port-D Power On Reset Clock Generator OSC Clock Generator OSCX 8-bit External Memory Bus PSG / PWM DAC ROM SRAM 256k bytes 2.5K bytes WDT
LCD Driver
Vout, Vlcd V1~V4 C1+, C1C2+, C2COM0~COM35 SEG0~SEG55
DMA
8-bit Static Base Timer 8-bit CPU
Port-C
Bank Control Logic
Interrupt Controller
Baud Rate Generator
SPI
Port-C
INTX/PC0 SCK/PC1 MISO/PC2 MOSI/PC3 SS/PC4 DATA_READY/PC5 TXD0/PC6 RXD0/PC7 TXD1/PD6 RXD1/PD7 LD[3:0]/PL3~0 CP/PL4 AC/PL5 LOAD1/PL6 FLM/PL7 POFF BLANK LOAD2
Port-C UART with IrDA Mode Port-D Chip Select Logic Clocking Output Timer 0/1/2/3 - 12 bit Port-L LCD Controller LCD Driver COM 35~0
Port-E Port-E Port-F
SEG 55~0
FIGURE 2-1 ST2602B Block Diagram
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ST2602B
3
n n n n n n n
FEATURES
Totally static 8-bit CPU ROM: 256k x 8-bit RAM: 2.5K x 8-bit Stack: Up to 128-level deep Operation voltage: 2.4V ~ 3.6V Operation frequency: - 3.0Mhz@2.4V(Min.) - 4.0Mhz@2.7V(Min.) LCD Drives - COM: 36 outputs. Eight shared with one output port - SEG: 56 outputs. Shared with 3 I/O ports and memory bus signals. One 8x8 Signed Multiplier Low Voltage Reset (LVR) - Two levels by code option Low Voltage Detector (LVD) - Programmable 4 levels - System power or external battery level can be detected. Programmable Watchdog Timer (WDT) Memory interface to ROM, RAM, Flash Memory configuration - Three kinds of banks for program, data and interrupt - 12-bit bank registers support up to 44M bytes - Six programmable chip-selects with 4 modes - Maximum single device of 16M bytes General-Purpose I/O (GPIO) ports - Up to 39 bit programmable I/Os 8 dedicated CMOS I/Os 23 shared with LCD SEGs 8 open drain output pins shared with LCD COMs - Bit programmable pull-up for input pins - Pull-up/down and open-drain/CMOS control for Port-C Timer/Counter - Four 12-bit timers. - One 8-bit base timer - Seven fixed base timers Three clocking outputs - Clock sources including Timer0/1, baud rate generator Eleven prioritized interrupts with dedicated exception vectors - External interrupt (edge triggered) - LCD buffer interrupt - Base timer interrupt - Timer0~3 interrupts (x4) - SPI interrupts (x2) - UART interrupts (x2) Dual clock sources with warm-up timer - Low frequency crystal oscillator (OSCX) **************************************************** 32768 Hz - High frequency resistor or crystal/resonator oscillator (OSC) selected by pin option .................. 455K~4M Hz n Direct Memory Access (DMA) - Block-to-Block transfer - Block to Single port n LCD Power Management - DC-DC converter with 8-level output control - LC driving voltage regulator with 16-level control - 1/4, 1/5, 1/6 bias options with 4 voltage followers n LCD Driver - 32x28~56x36 resolution, maximum 2016 dots - Clock source from OSC/OSCX. - Internal bias resistors(1/4, 1/5, 1/6 bias). n LCD Controller (LCDC) - Software programmable display size up to 160X120 - B/W, Hardware 4/16 gray levels with 5-bit palette - Support 1-/4-/8-bit LCD data bus - Share system memory with display buffer and with no loss of the CPU time - LCD buffer extension function to combine both internal and external RAM for larger display - Diverse functions including virtual screen, panning, scrolling, contrast control and alternating signal generator n Programmable Sound Generator (PSG) - Four channels with three playing modes: 9-bit ADPCM, 8-bit PCM and 8-bit melody - One 16-byte buffer and 6-bit volume control per channel - Wavetable melody support - Two dedicated PWM outputs for direct driving - One 12-bit current DAC n Universal Asynchronous Receiver/Transmitter (UART) - Full-duplex operation - Baud rate generator with one digital PLL - Standard baud rates of 600 bps to 115.2 kbps - Both transmitter and receiver buffers supported - Direct glueless support of IrDA physical layer protocol - Two sets of I/Os (TX,RX) for two independent devices n Serial Peripheral Interface (SPI) - Master and slave modes - Five serial signals including enable and data-ready - Both transmitter and receiver buffers supported - Programmable data length from 7-bit to 16-bit n Vlcd/LVD trimming fuse function: - Vlcd default voltage variation trimming. - 4-level LVD voltage variation trimming. n Three power down modes - WAI0 mode - WAI1 mode - STP mode
n n n n n n
n
n
n n
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ST2602B
4
SIGNAL DESCRIPTIONS
TABLE 4-1 Signal Function Groups Function Group Pad No. Designation Description VCC: Power supply for system Power VCC , PVCC, AVCC AVCC: Power supply for LCD function PVCC: Power supply for PSGO and PSGOB NOTE: PVCC level must not be higher than VDD level. GND: System power ground Ground GND , PGND, AGND AGND: Power ground for LCD function PGND: Power ground for PSGO and PSGOB RESET : Active low system reset signal input TEST: Leave this pin open when normal operation MMD/ CS0 : Memory modes selection pin RESET , System control TEST, MMD/ CS0 Normal mode: Enable internal ROM. MMD/ CS0 is connected to GND. Emulation mode: Disable internal ROM. MMD/ CS0 is connected to the chip-select pin of external ROM. During reset period, the MMD/ CS0 is an internally pulled-up input pin. After reset cycles, MMD/ CS0 is changed to be an output pin. It will output signal CS0 . High frequency oscillator (OSC) mode selected by code-option XIO,OSCI OSCXO,OSCXI, , Crystal mode: One crystal or resonator should be connected between OSCI and XIO Resistor oscillator mode: One resistor should be connected between OSCI and VCC OSCXI, OSCXO: Connect one 32768Hz crystal between these two pins when using low frequency oscillator WR / SEG9, External memory bus signals / LCD drivers PSG/PWM DAC Chip selects / LCD drivers UART RD / SEG8 A[22:0]/SEG32~SEG10 D[7:0]/SEG7~SEG0 PSGO, PSGOB External memory address bus / LCD Segment drivers External memory data bus / LCD Segment drivers PSG outputs. Connect to one buzzer or speaker I/O port D and chip-select outputs / LCD Segment drivers External memory R/W control signals / LCD Segment drivers
Clock
CS5 ~ 1 /PD4~0 / SEG37~SEG33,
CS6 /A23/PD5 /SEG38
RXD0/PC7,TXD0/PC6, RXD1/PD7/SEG40,TXD1/ PD6/SEG39
DATA_READY /PC5 , SS /PC4 , SDO/PC3 ,
UART signals and I/Os / LCD Segment drivers
SPI
SPI signals and I/Os
SDI/PC2 , SCK/PC1
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ST2602B
TABLE 4-2 Signal Function Groups (continued) Function Group External clock/signal interrupt Clocking output GPIO / LCD drivers Pad No. Designation INTX/PC0 BCO/PE2/SEG43 , TCO1/PE1/SEG42 , TCO0/PE0/SEG41 PE6~3/SEG47~SEG44 PL7~0/SEG55~SEG48 BLANK/COM0, POFF/COM1, FLM/COM2, LOAD1/COM3, LOAD2/COM4, AC/COM5,CP/COM6, EIO/COM7, LD7~LD0/COM15/COM8 Vout, Vlcd, V1, V2, V3, V4 C1+, C1-, C2+, C2VIN Description External interrupt inputs
Clocking outputs / LCD Segment drivers
I/O port E/ LCD Segment drivers I/O port L/ LCD Segment drivers LCD control signals
LCD control signals (for controller mode)
LCD voltage source LCD voltage booster Low Voltage Detector
LCD voltage sources Connect a 0.1 uF between C1+ and C1-, C2+ and C2repectively. Analog input pin of Low Voltage Dector module
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ST2602B
5
PAD DIAGRAM
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ST2602B
6
ELECTRICAL CHARACTERISTICS
*Note: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. All the ranges are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposed to the absolute maximum rating conditions for extended periods may affect device reliability.
6.1 Absolute Maximum Rations
DC Supply Voltage ---------------------------- -0.3V to +4.5V Operating Ambient Temperature ---------- -10C to +60C Storage Temperature ------------------------ -10C to +125C
6.2 DC Electrical Characteristics
Parameter Operating Voltage Operating Frequency Operating Frequency Operating Current Standby Current Standby Current Standby Current Standby Current Input High Voltage Symbol VCC F1 F2 IOP I SB0 I SB1 I SB2 I SB3 V IH 0.7Vcc 0.85Vcc Input Low Voltage V IL GND-0.3 0.3Vcc 0.15Vccc Pull-up resistance Output high voltage Output low voltage Output high voltage Output low voltage DAC current Low Voltage Detector current Vlcd variation INT LVD variation EXT LVD variation ILVR -3% -4% -4% R IH VOH1 VOL1 VOH2 VOL2 2.4mA 3 30 150 0.7Vcc 0.3Vcc 0.7Vcc 0.3Vcc 3.6mA 60 +3% +4% +4% Min. 2.4 2.7 Typ. 3.0 3.0 2.5 450 3.5 0.5 100 Max. 3.6 3.6 3 4 3 550 5 1 130 Vcc+0.3
Standard operation conditions: VCC = 3.0V, GND = 0V, TA = 25C, OSC = 4M Hz, unless otherwise specified Unit V V MHz MHz mA mA mA mA uA V V V V KW V V V V Fosc = 3MHz Fosc = 4MHz VCC = 2.4V ~ 3.6V VCC = 2.7 ~ 3.6V All I/O port are input and pull-up, execute NOP instruction, LCDC on All I/O port are input and pull-up, OSCX on, LCDC off (WAIT0 mode) All I/O port are input and pull-up, OSCX on, LCDC off (WAIT1 mode) All I/O port are input and pull-up, OSCX off, LCDC off (WAIT1 mode) LCD on, sysck = LCDCK = OSCX, OSC off, Wait0, no panel (fast B/W mode) Port-C/D/E/L RESET Port-C/D/E/L Condition
RESET
Port-C/D/E/L (input Voltage=0.7VCC) Port-C/D/L (IOH =-6mA) Port-C/D/E/L (IOL =9mA) PSG0/PSG0B( in PWM mode), I OH = 35mA. PSG0/PSG0B( in PWM mode), I OL = -65mA.
DAC output current of maxumum digital input value
mA mv mv mv Total LVD current consumption Default voltage of Vlcd variation sample by sample Internal LVD voltage variation sample by sample external LVD voltage variation sample by sample
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ST2602B
SPI clock frequency 4.0 MHz SPI slave mode
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ST2602B
6.3 AC Electrical Characteristics
FIGURE 6-1 External Read Timing Diagram
FIGURE 6-2 External Write Timing Diagram TABLE 6-1 Timing parameters for FIGURE 6-1 and FIGURE 6-2 Standard operation conditions: VCC = 3.0V, GND = 0V, TA = 25C
Symbol tSA tHA tWLC tCLWL tWHCH tSDW tHDW tCLRL tRHCH tSDR tHDR tR tF
Characteristic Address setup time Address hold time CS " pulse width L" CS asserted to WR asserted CS negated after WR is negated CS asserted to data-out is valid Data-out hold time after WR is negated CS asserted to RD asserted CS negated after RD is negated Data-in valid before RD is negated Data-in hold time after RD is negated Signal rise time Signal fall time
Min. -- 0 166 -- 10 -- 20 -- 10 30 10 -- --
Rating Typ. Max. -- 10 -- -- -- -- 1/2 tWLC -- -- -- 1/2 tWLC -- -- 1/2 tWLC -- -- -- 20 10 -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
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ST2602B
6.4 Characteristic Charts
Voltage & Frequency 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 2 2.5 3 Voltage
FIGURE 6-3 Frequency of R-OSC as a function of VCC
R=34K R=60.7k R=137k
MHz
3.5
4
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ST2602B
Fosc VS. Rosc
7.00
6.00
3V 2.7V 2.4V 3.3V 3.6V
5.00
MHz
4.00
3.00
2.00
1.00
0.00 10 100 1000
Kohm
FIGURE 6-4 Frequency of R-OSC as a function of Resistor
Voltage Frequency 4MHz 3MHz 2MHz 1MHz 3V 60K Ohm 90K Ohm 140K Ohm 300K Ohm
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ST2602B
7
APPLICATION CIRCUITS
ST2602B Application Circuit 1
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ST2602B
ST2602B Application Circuit 2
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ST2602B
ST2602B+ST8008+ST8009 Application Circuit
Note: LR pin of ST8008 is connected to GND. L/R bit of ST8009 is configured as low by " interface control selection" instruction
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ST2602B
8
FEATURE COMPARISON OF ST2600B SERIES
Part Number
ROM RAM Built-in LCD Driver Driving LCD with ext. driver Dedicated I/O LCD-Shared I/O LCD gray level PSG / volume-control DAC Low voltage detector Low voltage reset Watchdog timer Serieal interface LCDCK= 32KHz Trimming Fuse ST2608B 1M Byte 5K Byte 36 COMs X 72 SEGs ~9000 dots (16 gray) ~36000 dots (mono) 24 (PA, PC, PL) 32 (PB, PD, PE, PF) ST2604B ST2602B 512K Byte 256K Byte 3.5K Byte 2.5K Byte 36 COMs X 64 SEGs 36 COMs X 56 SEGs ~6000 dots (16 gray) ~4000 dots (16 gray) ~24000 dots (mono) ~16000 dots (mono) 16 (PA, PC) 8 (PC) 39 (PB[6:0], PD, PE, PL, PF) 31 (PD, PE[6:0], PL, PF) Up to 16 gray levels 4-channel wavetable / 64 levels 9-bit PWM, 12-bit current DAC Internal / External 4 levels Yes Yes UART, SPI, IrDA YES YES ST2601B 128K Byte 1.5K Byte 36 COMs X 56 SEGs ~2500 dots (16 gray) ~10000 dots (mono) 8 (PC) 31 (PD, PE[6:0], PL, PF)
Feature Comparison of ST2602 and ST2602B:
Part Number ROM RAM Built-in LCD Driver Driving LCD with ext. driver Dedicated I/O LCD-Shared I/O Basically functions LCFG and I/O configure LCDCK = 32KHz PSG volume maximum Vlcd variation(VDD=2.4~3.6) Vlcd default voltage variation Current consumption of LVD DAC ST2602 256K Byte 2.5K Byte 36 COMs X 56 SEGs ~4000 dots (16 gray) ~16000 dots (mono) 8 (PC) 31 (PD, PE[6:0], PL, PF) The same The same NO normal ~300mV -300mV~+300mV 200uA 10-bit ST2602B 256K Byte 2.5K Byte 36 COMs X 56 SEGs ~4000 dots (16 gray) ~16000 dots (mono) 8 (PC) 31 (PD, PE[6:0], PL, PF) The same The same YES 2-time larger than ST2062 ~30mV -90mV~+90mV 30uA 12-bit
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ST2602B
8.1 LCFG Setting Difference of ST2600 Series
ST2608/ST2608B
CFGS[2~0] 00X 010 011 100 101 110 111 SEG0~31 Pad Definition SEG32 SEG33~38 SEG39 SEG40 SEG41~47 SEG48~55 SEG0~71 SEG0~63 SEG0~55 SEG0~47 PD0~PD7 PD0~PD6 PD0~PD7 SEG56~63 SEG64~71 PE0~PE7 PE0~PE7 PE0~PE7 PE0~PE7 PE0~PE7
SEG0~31 No Use A/D Bus A/D Bus
No Use No Use SEG0~31 No Use PB0~PB7
PB0~PB7 PB0~PB7 PB0~PB7
ST2604B
CFGS[2~0] 000 001 010 011 100 101 110 111 Pad Definition SEG33~39 SEG40 SEG41~47 SEG48~55 SEG0 ~ 63 SEG0 ~ 39 PD7 PB0 ~ 6 PE0 ~ 7 SEG0 ~ 63 SEG0 ~ 55 SEG0 ~ 47 PE0 ~ 7 SEG0 ~ 31 A22 PD0 ~ 7 PB0 ~ 6 PE0 ~ 7 A/D bus PD0 ~ 7 PB0 ~ 6 PE0 ~ 7 A/D bus PD0 ~ 7 PB0 ~ 6 PE0 ~ 7 SEG0~31 SEG32 SEG56~63 PL0 ~ 7 PL0 ~ 7 PL0 ~ 7 PL0 ~ 7 PL0 ~ 7 PL0 ~ 7
ST2602/ST2602B
CFGS[2~0] 000 001 010 011 100 101 110 111 Pad Definition SEG33~39 SEG40 SEG41~47 SEG48~55 SEG0 ~ 55 SEG0 ~ 39 PD7 PE0 ~ 6 PL0 ~ 7 SEG0 ~ 55 SEG0 ~ 55 SEG0 ~ 47 PL0 ~ 7 SEG0 ~ 31 A22 PD0 ~ 7 PE0 ~ 6 PL0 ~ 7 A/D bus PD0 ~ 7 PE0 ~ 6 PL0 ~ 7 A/D bus PD0 ~ 7 PE0 ~ 6 PL0 ~ 7 SEG0~31 SEG32
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ST2602B
9
CHECKLIST Check List of ST2602B- 8-Bit Microcontroller With 256K Bytes ROM
CODE OPTION LOW VOLTAGE RESET
1.4 Volt
2.1 Volt
OSCILLATOR
32768 Hz Crystal R-OSC MHz (Resistor = Resonator Crystal MHz 2.4V ~ 3.6V Regulator 2.7V ~ 3.6V V
K )
OPERATING VOLTAGE
Other Range
~ 3.0 Mhz@2.4V
V
Note: Maximum operating frequency = 4.0 Mhz@2.7V, BATTERY POWER DOWN MODES CR20 WAI-0 x WAI-1 AAx AAAx
LOW VOLTAGE DETECTOR
Disabled Internal-LVD level1(2.4V) Internal-LVD level3(2.8V) External-LVD level1(1.2V) External-LVD level3(1.4V) Enabled, Baud Rate: Enabled, Bit Rate:
Internal-LVD level2(2.6V) Internal-LVD level4(3.0V) External-LVD level2(1.3V) External-LVD level4(1.5V) bps bps Disabled Disabled
UART SPI
ST2600B EV mode Selection Please check ST2600B DVB (PCB-300)
ST2602B EV mode: JP58 2a3
JP59 1a2
LCD SPECIFICATIONS
Resolution: Frame Rate:
x Hz
Duty: 1/ Bias: 1/ VLCD: V Alternation: Every Frame Lines ST8008x ST8009x 16 Gray-level ST8011x
Driver: ST8012x LCD Gray-level PSG mode Black and White
4 Gray-level
Current-type DAC PWM-single pin
PWM-two pin push pull PWM-two pin two end ,LXMAX= ,
Register Value
When playing sound: the PSGC = , When LCD is on: LCKR= , LCTR= , LFRA = LYMAX= , LPOW = LREG = , LCFG = When LVD is on: LVCTR = When power down: SYS = (WAIT0 or WAIT1)
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ST2602B
Data sheet CODE FILE: CHECK SUM: ST2602B user' manual Ver s .BIN H (Byte Mode) DATE(Y/M/D): 20 / /
Note: a. File format must be binary and the extension should be " .BIN" . b. File should be wrapped in ZIP format for transferring or e-mailing. c. Only single file is allowed. d. File length is 256K bytes. e. Functions should be checked on the emulation board or by real chip. f. Electric characteristics of the emulation board are not identical with those of the real chip. CUSTOMER COMPANY SIGNATURE SITRONIX FAE/SA SALSE
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ST2602B
Project Name
ITEM 1. 2. 3. 4.
DATE:
CHECK
NOTE
Make sure the resistor of R-OSC matches the desired frequency and VCC Make sure the referenced data sheet is the most updated version After power on, enter wait-0 mode for0.5 second before normal operation Initialize user RAM and every related control register Confirm Vlcd level, duty, bias, frame rate, alternating rate and the display quality of 5. LCD 6. Make sure to set LCKR=00h before turning off LCD function Make sure to implement a mechanism to fine-tune LCD contrast level. The 7. mechanism could be pin-option or keying-adjustment. 8. Confirm PSG output mode: Current DAC or one of three PWM modes Before entering power down mode, turn off unused peripheral such as LCD 9. controller, PSG, Current DAC and LVD Confirm I/O direction, default state and function-enable bits. Enable pull-up for 10. unused input pins Read from an input port after the signals are stable. Ex. when doing key scan, 11. delay 12 us from a new scan value then read the return lines. If an input connects to VCC or GND directly, make sure to remove any DC current 12. from internal pull-up/down resistor after the status is read. Do not use " read-modify-write" instructions, e.g. ROR and SMB0, to the registers that are read-only, write-only or have different functions for read and write. The registers at least include PA ~ PF, PL, PCL, PSGxA, PSGxB, TxCH, TxCL, PRS, 13. BTSR, BTC, MULL, MULH, MISC, SYS, IREQL, IREQH, LSSAL, LSSAH, LVPW, LCKR, LFRA, LPAL, SDATAH, SDATAL, SSR, DMSL, DMSH, DMDL, DMDH, DCNTL, DCNTH, LVCTR, UDATA and USR. RTI" instruction for unused interrupt vectors 14. Disable unused functions and reserve " Always disable interrupt function (by an `SEI' instruction) when modifying the 15. IENAL, IENAH, IREQL and IREQH registers. 16. Check stack memory is limited within 256 bytes. 17. Design a test mode to check every possible function 18. Follow the standard operation flow of using LCDCK=32KHz. Use ST2600B (enable ST2602B EV mode), to develop the whole system., and 19. verify every functions, especially sound quality and LCD performance. RC-type OSC has inter-sample variation. 20. For frequency-sensitive application (for example:IR communication and speech sampling rate), please use 32KHz_OSC to calibrate RC-type OSC by firmware 21. Fill up ROM until there has no empty place. (total 262144 bytes) 22. Make sure LCKR[5]=0
Engineer
Manager
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ST2602B
ST26xxB application note:
Content:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. PSG: Current-DAC and PWM application circuit Methods to make up LCD voltage deviation Vertical Cross talk on LCD display How to use IrDA mode to generate 38kHz carrier with data? LCDCK=32k clock source on ST2602B/ST2608B display System clock switching from OSC to OSCX Measure RC-OSC system clock IrDA mode application note ST26xx UART details IrDA BGRCK generation source OC-OSC / X'tal application circuit LCD blink cause by PSG How to measure the internal current of ST2600B? Ways to save power consumption 32KHz (OSCX) application circuit ST26XX+ST8008 CASCADE MODE CONNECTION Standard flow for switching I/O and segment LCDCK=32K with cascade mode User Manual for ST2600B external bus usage Pull-up resistance of D0~D7 for current issue when using ST75xx
Version 1.09
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ST2602B

Description: (These AP circuits are suitable for ST26xx series IC)
Figure 1 PWM mode application circuit
Figure 2 Current-DAC mode application circuit
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ST2602B

Notice1: In order to cover the variation of VLCD of LCD panel, be sure to reserve pin-option by GPIO to
change the status of VLCD( bit0:3 of register LREG). Here we suggest that there are at least 5-level of voltage pin-option for VLCD. If the GPIO is not enough to make pin-option, programmer can use key-return-line method for power on pin-option. For example: make pin-option for change VLCD at... /5.6/5.8/6.0V/6.2V/6.4/...
Notice2: Programmer should add a contrast controller function to adjust VLCD for the convenience of
end-user to change the contrast as they like. For example: VLCD is pre-set at 6.2 by pin-option, end-users can also adjust the contrast... /5.8/5.9V/6.0V/6.2V/6.2V/6.3/6.4/... by using contrast controller function.
Notice3: Verifying the performance of voice on ST2602/2604/2608 DEMO boards.
Because ST2600B DVB can not provide the totally voice efficacy, such like the volume and the quality of voice. So we strongly suggest to verify voice playing on ST2602B/ST2608B DEMO boards before MASK. (Ps... Because LCD SEG pins are shared with external EPROM, so the picture can not be verified on DEMO boards.)

Description: Vertical Cross talk on LCD display
Solution: Vertical cross talk usually happens when the differential voltage of V0~V4 are not closely. In this case,
increase C0~C4 (recommend > 1uF) will eliminate this problem. Fine tuning the value of capacitance to get the best LCD quality.
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ST2602B

Port-E-2 (PE2) is shared with clock signal output function, and the frequency of this pin is programmable. Programmer can define which signal pattern is "0", and which signal is "1" For example, using Timer_interrupt to enable/disable PE2 function, and programmers can produce the signal pattern which means "0" or "1" The same way, receive side can decode the signal by encode information.
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ST2602B
ST2602B/ST2608B display>
(1) Control register Address Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 $047 LCTR LPWR BLNK REV CAS GL[3] R/W Bit 3~2: GL[3:2] : LCD gray-level selection bit 00 = B/W. 01 = 4 gray 10 = 16gray 11 = fast B/W mode (2) Address Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 $048 LCKR W LMOD[1] LMOD[0] LCK[3] Bit [5:4]: LMOD : LCD data bus mode selection 00 = 1-bit mode 01 = 4-bit mode 1X = 8-bit mode Bit 2 GL[2] Bit 1 GL[1] Bit 0 GL[0] Default 1000 0000
Bit 2 LCK[2]
Bit 1 LCK[1]
Bit 0 LCK[0]
Default - - 00 0000
Bit 3~0: LCKR[3:0] : LCD clock selection (when SYSCK=OSCK) LCKR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 LCDCK (B/W, 4G, 16G mode) LCDCK (fast B/W mode) 1-bit mode 4-bit mode 8-bit mode 1-bit mode 4-bit mode 8-bit mode (LMOD=00) (LMOD=01) (LMOD=1X) (LMOD=00) (LMOD=01) (LMOD=1X) SYSCK SYSCK/8 SYSCK/2 SYSCK/16 SYSCK /4 SYSCK /32 SYSCK /6 SYSCK /48 SYSCK /8 SYSCK /64 SYSCK /10 SYSCK /80 SYSCK /12 SYSCK /96 SYSCK /14 SYSCK /112 SYSCK /16 SYSCK /128 SYSCK /18 SYSCK /144 SYSCK /20 SYSCK /160 SYSCK /22 SYSCK /176 SYSCK /24 SYSCK /192 SYSCK /26 SYSCK /208 SYSCK /28 SYSCK /224 SYSCK /30 SYSCK /240
(3) Sysclk is RC: 1. Lcd clock source is Sysclk. If Sysclk is RC, LCD clock source will be RC. 2. In ST2602B, if LCD clock source is RC, B/W, 4G, 16G mode are the same as ST2602. 3. The fast B/W mode is added. In fast B/W mode, the LCDCK will be divided by 8. 4. IF Sysclk is RC and in fast B/W mode, the frame rate is determined as below.
Frame Rate =
LCDCK ( LXMAX + LFRA + 1) x ( LYMAX * 2)
(4) Sysclk is 32K: 1. If Sysclk is 32k, LCD clock source will be 32k. 2. If Sysclk is 32k, LCD can only display B/W. 3. If LCD clock source is 32k, please set GL[3:2]=11(fash B/W mode) . In this condition, LCKR and LPAN control registers will avoid. LCDCK is always 32k hz and the frame rate is only controlled by LFRA control register. 4. If LCD clock source is 32k, DC-DC converter clock (LPCK) will also become 32k. So, user must to change LPCK register to get higher pump frequency(We will provide a macro to take care this part). 5. IF Sysclk is 32K and in fast B/W mode, the frame rate is determined by below equation.
Frame Rate =
LCDCK , where LCDCK is 32K hz. ( LXMAX + LFRA + 1) x ( LYMAX * 2)
(5) change Sysclk from RC to 32K Step1: let LCD in fast B/W mode Step2: use the macro " SWITCH_SYSCLK_RC_TO_32K" to change Sysclk to 32K (6) change Sysclk from 32K to RC
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Step1: use the macro " SWITCH_SYSCLK_32K_TO_RC " to change Sysclk to RC (7) sample code 1. When B/W, 4G, 16G mode change to fast B/W mode or fast B/W mode change to B/W, 4G, 16G mode, must turn off LCD. for example: B/W, 4G, 16G mode change to fast B/W mode. ;====Step1 LCD OFF === LDA LCTR ORA #10000000B STA LCTR ;====Step2 set GL[3:2]=11, fast B/W mode === LDA LCTR ORA #00001100B STA LCTR ;=== Step3 set Frame rate about 65 Hz === LDA #6 ;when Sysclk is changed to 32k, LFRA can' be modified. Thus LFRA t STA LFRA ;is determined by equation2. Let the frame rate in sysclk=32k mode is ;about 65hz LDA #00001000B ;since LFRA has been determined, LCKR is determined by frame rate equation. STA LCKR ;Let the frame rate in Sysclk=RC mode is about 65hz ;===Step4 LCD ON === LDA LCTR AND #~10000000B STA LCTR [After setting up fast B/W mode, then switch SYSCK from RC to 32k] 2. Sysck from RC change to 32k... Please use the macro " SWITCH_SYSCLK_RC_TO_32K" . This macro will use 4 bytes RAM. They are show below. ;===== used ram ==== LCD_FLAG DS 1 IENAL_BAK DS 1 IENAH_BAK DS 1 LPCK_BAK DS 1 And this macro will also use LCD interrupt. Please copy below program in LCD interrupt service routine. ;==== LCD interrupt service routine === LCDFR_ISR: PHA LDA #FFH STA LCD_FLAG RMB7 IENAL ;DISABPLE LCD INTERRUPT PLA RTI The declaration of this macro is show below (please don' modify this macro) t SWITCH_SYSCLK_RC_TO_32K .MACRO ;=== backup LPCK === LDA LPCK STA LPCK_BAK LDA #2 STA LPCK ;=== BACKUP IENAL/H AND ONLY ENABLE LCD INT === SEI LDA IENAL STA IENAL_BAK LDA IENAH STA IENAH_BAK LDA #10000000B ;ONLY ENABLE LCD INT STA IENAL STZ IENAH LDA #01111111B
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STA IREQL STZ LCD_FLAG CLI ?WAIT_LCD_INT_RC232K: LDA LCD_FLAG BEQ ?WAIT_LCD_INT_RC232K ;=== change SYSCLK = 32K === LDA SYS ORA #10000000B STA SYS NOP NOP NOP BBR7 SYS,$ ;=== RECOVERY IENAL/H === SEI LDA IENAL_BAK STA IENAL LDA IENAH_BAK STA IENAH CLI .ENDM 3. Sysck from 32K change to RC. (After changing to RC, LCD must be in fast B/W mode.) Please use the macro " SWITCH_SYSCLK_32K_TO_RC" . SWITCH_SYSCLK_32K_TO_RC .MACRO ;=== BACKUP IENAL/H AND ONLY ENABLE LCD INT === SEI LDA IENAL STA IENAL_BAK LDA IENAH STA IENAH_BAK LDA #10000000B ;ONLY ENABLE LCD INT STA IENAL STZ IENAH LDA #01111111B STA IREQL ;CLEAR LCD INT REQUEST STZ LCD_FLAG CLI ?WAIT_LCD_INT_32K2RC: LDA LCD_FLAG BEQ ?WAIT_LCD_INT_32K2RC ;=== change SYSCLK = RC === LDA SYS AND #~10000000B STA SYS NOP NOP NOP BBS7 SYS,$ ;=== RECOVERY IENAL/H === SEI LDA IENAL_BAK STA IENAL LDA IENAH_BAK STA IENAH CLI LDA LPCK_BAK STA LPCK .ENDM ;CLEAR LCD INT REQUEST
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Cause warm-up time is different when OSC is RC-OSC or X' tal. To make sure the system clock has switched to OSCX, or error will happen. Sample code, please follow up... LDA SYS ORA #80H STA SYS ;switch OSC to OSCX NOP NOP NOP BBR7 SYS,$ ; branch self until OSC is changed to OSCX

Since programmer wants to measure the system clock when using RC-OSC, please follow up. Please connect a 3K-Ohm resistor between Vdd and XIO. You can get a periodic signal output from the XIO pin. It's RC osc signal.

Since IrDA has strictly protocol when transmit/receive data. We suggest programmers use X'tal to be system clock instead of RC-OSC if IrDA signals are needed. Programmer can use ceramic-OSC to gain some profit since it' cheaper than X' s tal.
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comes from OSC(main frequency) and fine tuning by 32768Hz crystal(REF) to make output baud rate is a stable frequency signal and will not effected by VDD variation.( RC-OSC frequency will change when VDD changes.)
BGRCK: BGRCK is used to produce UART baud rate, and BGRCK
Baud rate: Baud rate comes from BGRCK, and is determined by BDIV and BRS registers. The "Error rate"
of baud rate is the maximum positive/negative inaccuracy of output baud rate. For example: If baud rate = 9600bps and OSC is in the rage of 3.72~4.28MHz, programmer should set BRS=61, BDIV=13
to get the best output baud rate which has error of 0.1%.So the real output baud rate will be in the range of [9600x0.999:9600x1.001].
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< IrDA BGRCK generation source >
BGRCK can be generated by two ways. 1. When bit7 of BCTR is 0,Haredware PLL which is used to stable BGRCK output will be operated. Cause BGRCK comes from OSC, since RC-OSC can' produce stable frequency, ST26xx hardware will fine tune t BGRCK output frequency referenced from 32768Hz crystal to make BGRCK is in the range no matter VDD variation. 2. When bit7 of BCTR is 1: It' used when OSC is X' Since X' can produce stable frequency, and BGRCK comes from OSC, so s tal. tal BGRCK will also be stable if OSC is X' Programmer can get better BGRCK output to make UART signal tal. much more accurate by this way. When bit7 of BCTR is 1, UART baud rate will be get in the following formula: baud rate = Sysclk/(BDIV*16) (no need to set "BRS")
< How to avoid LCD blink caused by PSG >
Description: LCD display may blink when LCD function and PSG function are playing in the same time. LCD blink caused by CPU can ' t stand the load of calculation. So the LCD display my lag. And We can find there has blink problem. Solution: By using internal DMA function to move LCD data instead of programming method can solve part of this kind of problem. If there still has the same problem, we can separate LCD data into 16 parts and use DMA method to move into LCD RAM. The LCD blink problem can be totally solved. Example program can be found by SA engineer. !!Please email us!!!
< How to measure the internal current of ST2600B?>
When finish developing program by ST2600B, programmer should measure the current consumption of totally possible situations. In that time programmer can use ST2600B stand alone mode with running external ROM. In order to only measure the current from IC, the power for External ROM should be independent. And then we can measure the current from IC only!!
< Ways to save power consumption >
There are some factors which can effect current consumption... (1) Main-frequency : Higher frequency needs more current (2) DAC mode cost much current than PWM mode (3) Vlcd voltage level : Higher Vlcd pays higher current. (4) Using EPROM will cost more current than no use. (5) Input without any connection will randomly cost power (6) WAIT mode with considerable program can save lots of power (7) Larger panel will pay more current. (8) Un-ideal hardware connection will cause unknown current waste.
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<32KHz (OSCX) application circuit >
Below shows the application circuit of 32KHz X' connection. Please follow it. tal The original application circuit as below:
The modified circuit as follow:

This interface is suitable for ST26xx series IC. Notice: ST26xxB can only output common signal when cascade mode. User can not mix the segment from ST26xxB and the segment from other LCD drivers. It' because the LCD s driving ability of ST26xxB and other LCD drivers are not the same. If user mix them, the performance of LCD display may be bad. (Color block or cross-talk)
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< Standard flow for switching I/O and segment >
We know that there are many I/O which are shared with LCD segment. And the configure is determined by LCFG register. Here is the standard flow of configure I/O or segment, please follow up. Or programmer will not configure I/O possibly. (1) Please configure LCFG first!! (2) And then configure PCA/PCB/PCC/PCD/PCE/PCL (3) Finally configure PA/PB/PC/PD/PE/PL Sample code: LDA #FFH STA LCFG STA PCL STA PL
; enable all I/O ; configure PL as output ; PL0~PL7 high status
< LCDCK=32K with cascade mode >
There has some limit when programmer use LCDCK=32K and cascade.
Programmer can use ST26 with LCD cascade mode, it's no doubt. Also, programmer can use cascade mode combine with LCDCK from 32KHz(OSCX). But user should take care one thing as following: We know ST26 can support Cascade 1/2/4-bit data bus mode, however, LCDCK=32K function can only support 8-bit mode!! So, when programmer use these two functions in the same time, MCU will push 8-bit data per clock cause LCDCK=32K function, but cascade mode maximum push 4-bit data out to LCD driver per clock, so you will lose 4-bit data(bit4~bit7) and make display data wrong.
The solution is to modify the picture, let MCU push 8-bit every clock, and we separate it every 4-bit data into 8 bit data as picture 2. and we can solve it. Mention that because LCDCK=32K can maximum load 36 x 80 dots picture, by above condition, we finally can push 36x40 dots picture to show on LCD since we only use half of data (first 4-bit).
The original picture information
bit0~bit7 bit8~bit15 bit16~bit23
picture 2 : modified picture
Notice: ST26xxB can only output common signal when cascade mode. User can not mix the segment from ST26xxB and the segment from other LCD drivers. It' because the LCD s driving ability of ST26xxB and other LCD drivers are not the same. If user mix them, the performance of LCD display may be bad. (Color block or cross-talk)
< User Manual for ST2600B external bus usage > [Description]
Since users may use external memory bus to access external ROM, FLASH, or LCD driver, we draw this manual to tell the
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details and notice when using external bus by ST2600B in two mode: (1)Stand alone mode (2) ICE-mode (1) When using ST2600B Stand alone mode: External memory bus can be output directly by ST2600B DVB (PCB-300) J22 pin-1 to pin-32 (2) When using ST2600B ICE mode: Because external data can be controlled by PC through ST-ICE, so the external bus will be shared with ICE connector pins (PCB-300 - J15) (a) Please first amount 74hc32 on U11 and U12. (b) PCB-300 J15 pins allocation as following:
(c) ST2600B DVB should be connected to ST-ICE by J15, and also be connected to external bus by above table
< Pull-up resistance of D0~D7 for current issue when using ST75xx >
Description: When entering sleep mode, D0~D7 of ST75xx will be floating, and make current consumption (about 120uA). It can be solved by adding 8 1M-ohm resistance on D0~D7.
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10
REVISIONS
PAGE DATE
2009/3/9 V1.0 V1.1 Add ST26xx application note
REVISION DESCRIPTION
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. Sitronix Technology Corp. reserves the right to change this document without prior notice and makes no warranty for any errors which may appear in this document. Sitronix products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where products failure could result in injury, or loss of life, or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. Page 34/34

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